LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT stos
    PORT(
         X : IN  std_logic;
         WR : IN  std_logic;
         RE : IN  std_logic;
         Y : OUT  std_logic;
         FULL : OUT  std_logic;
         EMPTY : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal X : std_logic := '0';
   signal WR : std_logic := '0';
   signal RE : std_logic := '0';

 	--Outputs
   signal Y : std_logic;
   signal FULL : std_logic;
   signal EMPTY : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   constant period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: stos PORT MAP (
          X => X,
          WR => WR,
          RE => RE,
          Y => Y,
          FULL => FULL,
          EMPTY => EMPTY
        );

   -- Clock process definitions
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		X <= '1';
		WR <= '1';
      wait for period*10;
		WR <= '0';

		wait for 100 ns;	
		X <= '0';
		WR <= '1';
      wait for period*10;
		WR <= '0';
		
		wait for 100 ns;	
		RE <= '1';
      wait for period*10;
		RE <= '0';
		
		wait for 100 ns;	
		RE <= '1';
      wait for period*10;
		RE <= '0';
      -- insert stimulus here 

      wait;
   end process;