library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity stos is
    Port ( X : in  STD_LOGIC;
           WR : in  STD_LOGIC;
           RE : in  STD_LOGIC;
           Y : out  STD_LOGIC := '0';
           FULL : out  STD_LOGIC;
           EMPTY : out  STD_LOGIC);
end stos;

architecture Behavioral of stos is

signal stos: STD_LOGIC_VECTOR(7 downto 0);
signal i : integer := 0;
signal s : STD_LOGIC := '0';
signal k : STD_LOGIC := '0';
begin
	main : process(WR,RE)
			begin
			-- Pisanie
			if WR = '1' and s = '0' then
				stos(i) <= X;
				s <= '1';
				i <= i + 1;
			end if;
			if WR = '0' and s = '1' then
				s <= '0';
			end if;
			-- Czytanie
			if RE = '1' and k = '0' then
				k <= '1';
				Y <= stos(i);
				i <= i - 1;
			end if;
			if RE = '0' and k = '1' then
				k <= '0';
			end if;
			-- Sprawdzanie stanu stosu
			if i = 0 then
				EMPTY <= '1';
			else
				EMPTY <= '0';
			end if;
			if i = 7 then
				FULL <= '1';
			else
				FULL <= '0';
			end if;
	end process main;
	
end Behavioral;